`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:32:21 11/13/2011 
// Design Name: 
// Module Name:    exerciser 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ExerciserDevice(
  input           CLK,
  input           RST,

  input   [31:0]  S_AWADDR,
  input           S_AWVALID,
  output          S_AWREADY,
  input   [31:0]  S_WDATA,
  input   [3:0]   S_WSTRB,
  input           S_WVALID,
  output          S_WREADY,
  output  [1:0]   S_BRESP,
  output          S_BVALID,
  input           S_BREADY,
  input   [31:0]  S_ARADDR,
  input           S_ARVALID,
  output          S_ARREADY,
  output  [31:0]  S_RDATA,
  output  [1:0]   S_RRESP,
  output          S_RVALID,
  input           S_RREADY,

  input           S_TVALID,
  output          S_TREADY,
  input   [127:0] S_TDATA,
  input   [3:0]   S_TSTRB,
  input   [47:0]  S_TUSER,
  input           S_TLAST,

  output          M_TVALID,
  input           M_TREADY,
  output  [127:0] M_TDATA,
  output  [3:0]   M_TSTRB,
  output  [47:0]  M_TUSER,
  output          M_TLAST,

  output  [0:0]   M_AWID,
  output  [31:0]  M_AWADDR,
  output  [7:0]   M_AWLEN,
  output  [2:0]   M_AWSIZE,
  output  [1:0]   M_AWBURST,
  output          M_AWVALID,
  input           M_AWREADY,
  output  [127:0] M_WDATA,
  output  [15:0]  M_WSTRB,
  output          M_WLAST,
  output          M_WVALID,
  input           M_WREADY,
  input   [0:0]   M_BID,
  input   [1:0]   M_BRESP,
  input           M_BVALID,
  output          M_BREADY,
  output  [0:0]   M_ARID,
  output  [31:0]  M_ARADDR,
  output  [7:0]   M_ARLEN,
  output  [2:0]   M_ARSIZE,
  output  [1:0]   M_ARBURST,
  output          M_ARVALID,
  input           M_ARREADY,
  input   [0:0]   M_RID,
  input   [127:0] M_RDATA,
  input   [1:0]   M_RRESP,
  input           M_RLAST,
  input           M_RVALID,
  output          M_RREADY
  );

  wire          ex_s_tvalid;
  wire          ex_s_tready;
  wire [127:0]  ex_s_tdata;
  wire [3:0]    ex_s_tstrb;
  wire          ex_s_tlast;
  wire          ex_m_tvalid;
  wire          ex_m_tready;
  wire [127:0]  ex_m_tdata;
  wire [3:0]    ex_m_tstrb;
  wire          ex_m_tlast;

  InternalDevice 
  idev(
    .CLK            (CLK     ),
    .RST            (RST     ),

    .M_PRI_TVALID   (M_TVALID),
    .M_PRI_TREADY   (M_TREADY),
    .M_PRI_TDATA    (M_TDATA ),
    .M_PRI_TSTRB    (M_TSTRB ),
    .M_PRI_TLAST    (M_TLAST ),
    .S_PRI_TVALID   (S_TVALID),
    .S_PRI_TREADY   (S_TREADY),
    .S_PRI_TDATA    (S_TDATA ),
    .S_PRI_TSTRB    (S_TSTRB ),
    .S_PRI_TLAST    (S_TLAST ),

    .M_SEC_TVALID   (ex_s_tvalid),
    .M_SEC_TREADY   (ex_s_tready),
    .M_SEC_TDATA    (ex_s_tdata),
    .M_SEC_TSTRB    (ex_s_tstrb),
    .M_SEC_TLAST    (ex_s_tlast),
    .S_SEC_TVALID   (ex_m_tvalid),
    .S_SEC_TREADY   (ex_m_tready),
    .S_SEC_TDATA    (ex_m_tdata),
    .S_SEC_TSTRB    (ex_m_tstrb),
    .S_SEC_TLAST    (ex_m_tstrb)
  );

  AxisRecordPlayer 
  arp(
    .CLK            (CLK      ),
    .RST            (RST      ),

    .S_AWADDR       (S_AWADDR ),
    .S_AWVALID      (S_AWVALID),
    .S_AWREADY      (S_AWREADY),
    .S_WDATA        (S_WDATA  ),
    .S_WSTRB        (S_WSTRB  ),
    .S_WVALID       (S_WVALID ),
    .S_WREADY       (S_WREADY ),
    .S_BRESP        (S_BRESP  ),
    .S_BVALID       (S_BVALID ),
    .S_BREADY       (S_BREADY ),
    .S_ARADDR       (S_ARADDR ),
    .S_ARVALID      (S_ARVALID),
    .S_ARREADY      (S_ARREADY),
    .S_RDATA        (S_RDATA  ),
    .S_RRESP        (S_RRESP  ),
    .S_RVALID       (S_RVALID ),
    .S_RREADY       (S_RREADY ),

    .S_TVALID       (ex_s_tvalid),
    .S_TREADY       (ex_s_tready),
    .S_TDATA        (ex_s_tdata),
    .S_TSTRB        (ex_s_tstrb),
    .S_TLAST        (ex_s_tlast),
    .M_TVALID       (ex_m_tvalid),
    .M_TREADY       (ex_m_tready),
    .M_TDATA        (ex_m_tdata),
    .M_TSTRB        (ex_m_tstrb),
    .M_TLAST        (ex_m_tlast),

    .M_ARID         (M_ARID   ),
    .M_ARADDR       (M_ARADDR ),
    .M_ARLEN        (M_ARLEN  ),
    .M_ARSIZE       (M_ARSIZE ),
    .M_ARBURST      (M_ARBURST),
    .M_ARVALID      (M_ARVALID),
    .M_ARREADY      (M_ARREADY),
    .M_RID          (M_RID    ),
    .M_RDATA        (M_RDATA  ),
    .M_RRESP        (M_RRESP  ),
    .M_RLAST        (M_RLAST  ),
    .M_RVALID       (M_RVALID ),
    .M_RREADY       (M_RREADY ),
    .M_AWID         (M_AWID   ),
    .M_AWADDR       (M_AWADDR ),
    .M_AWLEN        (M_AWLEN  ),
    .M_AWSIZE       (M_AWSIZE ),
    .M_AWBURST      (M_AWBURST),
    .M_AWVALID      (M_AWVALID),
    .M_AWREADY      (M_AWREADY),
    .M_WDATA        (M_WDATA  ),
    .M_WSTRB        (M_WSTRB  ),
    .M_WLAST        (M_WLAST  ),
    .M_WVALID       (M_WVALID ),
    .M_WREADY       (M_WREADY ),
    .M_BID          (M_BID    ),
    .M_BRESP        (M_BRESP  ),
    .M_BVALID       (M_BVALID ),
    .M_BREADY       (M_BREADY )
  );

endmodule
